Commit 4f2331e5 authored by Aurelien Jarno's avatar Aurelien Jarno Committed by Richard Henderson
Browse files

tcg: implement real ext_i32_i64 and extu_i32_i64 ops 



Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a
32-bit value is always converted to a 64-bit value and not propagated
through the register allocator or the optimizer.

Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Stefan Weil <sw@weilnetz.de>
Acked-by: default avatarClaudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 6acd2558

tcg/aarch64/tcg-target.c

+4 −0
Original line number Diff line number Diff line
@@ -1556,6 +1556,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_ext16s_i32:

        tcg_out_sxt(s, ext, MO_16, a0, a1);

        break;

    case INDEX_op_ext_i32_i64:

    case INDEX_op_ext32s_i64:

        tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);

        break;
@@ -1567,6 +1568,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_ext16u_i32:

        tcg_out_uxt(s, MO_16, a0, a1);

        break;

    case INDEX_op_extu_i32_i64:

    case INDEX_op_ext32u_i64:

        tcg_out_movr(s, TCG_TYPE_I32, a0, a1);

        break;
@@ -1712,6 +1714,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = { 
    { INDEX_op_ext8u_i64, { "r", "r" } },

    { INDEX_op_ext16u_i64, { "r", "r" } },

    { INDEX_op_ext32u_i64, { "r", "r" } },

    { INDEX_op_ext_i32_i64, { "r", "r" } },

    { INDEX_op_extu_i32_i64, { "r", "r" } },



    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },

    { INDEX_op_deposit_i64, { "r", "0", "rZ" } },

tcg/i386/tcg-target.c

+5 −0
Original line number Diff line number Diff line
@@ -2064,9 +2064,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_bswap64_i64:

        tcg_out_bswap64(s, args[0]);

        break;

    case INDEX_op_extu_i32_i64:

    case INDEX_op_ext32u_i64:

        tcg_out_ext32u(s, args[0], args[1]);

        break;

    case INDEX_op_ext_i32_i64:

    case INDEX_op_ext32s_i64:

        tcg_out_ext32s(s, args[0], args[1]);

        break;
@@ -2201,6 +2203,9 @@ static const TCGTargetOpDef x86_op_defs[] = { 
    { INDEX_op_ext16u_i64, { "r", "r" } },

    { INDEX_op_ext32u_i64, { "r", "r" } },



    { INDEX_op_ext_i32_i64, { "r", "r" } },

    { INDEX_op_extu_i32_i64, { "r", "r" } },



    { INDEX_op_deposit_i64, { "Q", "0", "Q" } },

    { INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } },

tcg/ia64/tcg-target.c

+4 −0
Original line number Diff line number Diff line
@@ -2148,9 +2148,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_ext16u_i64:

        tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);

        break;

    case INDEX_op_ext_i32_i64:

    case INDEX_op_ext32s_i64:

        tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);

        break;

    case INDEX_op_extu_i32_i64:

    case INDEX_op_ext32u_i64:

        tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);

        break;
@@ -2301,6 +2303,8 @@ static const TCGTargetOpDef ia64_op_defs[] = { 
    { INDEX_op_ext16u_i64, { "r", "rZ"} },

    { INDEX_op_ext32s_i64, { "r", "rZ"} },

    { INDEX_op_ext32u_i64, { "r", "rZ"} },

    { INDEX_op_ext_i32_i64, { "r", "rZ" } },

    { INDEX_op_extu_i32_i64, { "r", "rZ" } },



    { INDEX_op_bswap16_i64, { "r", "rZ" } },

    { INDEX_op_bswap32_i64, { "r", "rZ" } },

tcg/ppc/tcg-target.c

+6 −0
Original line number Diff line number Diff line
@@ -2200,12 +2200,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, 
    case INDEX_op_ext16s_i64:

        c = EXTSH;

        goto gen_ext;

    case INDEX_op_ext_i32_i64:

    case INDEX_op_ext32s_i64:

        c = EXTSW;

        goto gen_ext;

    gen_ext:

        tcg_out32(s, c | RS(args[1]) | RA(args[0]));

        break;

    case INDEX_op_extu_i32_i64:

        tcg_out_ext32u(s, args[0], args[1]);

        break;



    case INDEX_op_setcond_i32:

        tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
@@ -2482,6 +2486,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { 
    { INDEX_op_ext8s_i64, { "r", "r" } },

    { INDEX_op_ext16s_i64, { "r", "r" } },

    { INDEX_op_ext32s_i64, { "r", "r" } },

    { INDEX_op_ext_i32_i64, { "r", "r" } },

    { INDEX_op_extu_i32_i64, { "r", "r" } },

    { INDEX_op_bswap16_i64, { "r", "r" } },

    { INDEX_op_bswap32_i64, { "r", "r" } },

    { INDEX_op_bswap64_i64, { "r", "r" } },

tcg/s390/tcg-target.c

+5 −0
Original line number Diff line number Diff line
@@ -2090,6 +2090,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_ext16s_i64:

        tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);

        break;

    case INDEX_op_ext_i32_i64:

    case INDEX_op_ext32s_i64:

        tgen_ext32s(s, args[0], args[1]);

        break;
@@ -2099,6 +2100,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_ext16u_i64:

        tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);

        break;

    case INDEX_op_extu_i32_i64:

    case INDEX_op_ext32u_i64:

        tgen_ext32u(s, args[0], args[1]);

        break;
@@ -2251,6 +2253,9 @@ static const TCGTargetOpDef s390_op_defs[] = { 
    { INDEX_op_ext32s_i64, { "r", "r" } },

    { INDEX_op_ext32u_i64, { "r", "r" } },



    { INDEX_op_ext_i32_i64, { "r", "r" } },

    { INDEX_op_extu_i32_i64, { "r", "r" } },



    { INDEX_op_bswap16_i64, { "r", "r" } },

    { INDEX_op_bswap32_i64, { "r", "r" } },

    { INDEX_op_bswap64_i64, { "r", "r" } },