Commit 609ad705 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32 



Rather than allow arbitrary shift+trunc, only concern ourselves
with low and high parts.  This is all that was being used anyway.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 870ad154

target-tricore/translate.c

+6 −6
Original line number Diff line number Diff line
@@ -457,11 +457,11 @@ gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 
    tcg_gen_xor_i64(t1, result, r1);

    tcg_gen_xor_i64(t0, r1, r2);

    tcg_gen_andc_i64(t1, t1, t0);

    tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);

    tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);

    /* calc SV bit */

    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);

    /* calc AV/SAV bits */

    tcg_gen_trunc_shr_i64_i32(temp, result, 32);

    tcg_gen_extrh_i64_i32(temp, result);

    tcg_gen_add_tl(cpu_PSW_AV, temp, temp);

    tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);

    /* calc SAV */
@@ -1273,7 +1273,7 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 
    tcg_gen_xor_i64(t3, t4, t1);

    tcg_gen_xor_i64(t2, t1, t2);

    tcg_gen_andc_i64(t3, t3, t2);

    tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);

    tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);

    /* We produce an overflow on the host if the mul before was

       (0x80000000 * 0x80000000) << 1). If this is the

       case, we negate the ovf. */
@@ -1630,11 +1630,11 @@ gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 
    tcg_gen_xor_i64(t1, result, r1);

    tcg_gen_xor_i64(t0, r1, r2);

    tcg_gen_and_i64(t1, t1, t0);

    tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);

    tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);

    /* calc SV bit */

    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);

    /* calc AV/SAV bits */

    tcg_gen_trunc_shr_i64_i32(temp, result, 32);

    tcg_gen_extrh_i64_i32(temp, result);

    tcg_gen_add_tl(cpu_PSW_AV, temp, temp);

    tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);

    /* calc SAV */
@@ -2126,7 +2126,7 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 
    tcg_gen_xor_i64(t3, t4, t1);

    tcg_gen_xor_i64(t2, t1, t2);

    tcg_gen_and_i64(t3, t3, t2);

    tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);

    tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);

    /* We produce an overflow on the host if the mul before was

       (0x80000000 * 0x80000000) << 1). If this is the

       case, we negate the ovf. */

tcg/README

+10 −4
Original line number Diff line number Diff line
@@ -314,11 +314,17 @@ This operation would be equivalent to 


  dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)



* trunc_shr_i64_i32 t0, t1, pos

* extrl_i64_i32 t0, t1



For 64-bit hosts only, right shift the 64-bit input T1 by POS and

truncate to 32-bit output T0.  Depending on the host, this may be

a simple mov/shift, or may require additional canonicalization.

For 64-bit hosts only, extract the low 32-bits of input T1 and place it

into 32-bit output T0.  Depending on the host, this may be a simple move,

or may require additional canonicalization.



* extrh_i64_i32 t0, t1



For 64-bit hosts only, extract the high 32-bits of input T1 and place it

into 32-bit output T0.  Depending on the host, this may be a simple shift,

or may require additional canonicalization.



********* Conditional moves

tcg/aarch64/tcg-target.h

+2 −1
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ typedef enum { 
#define TCG_TARGET_HAS_muls2_i32        0

#define TCG_TARGET_HAS_muluh_i32        0

#define TCG_TARGET_HAS_mulsh_i32        0

#define TCG_TARGET_HAS_trunc_shr_i64_i32 0

#define TCG_TARGET_HAS_extrl_i64_i32    0

#define TCG_TARGET_HAS_extrh_i64_i32    0



#define TCG_TARGET_HAS_div_i64          1

#define TCG_TARGET_HAS_rem_i64          1

tcg/i386/tcg-target.h

+2 −1
Original line number Diff line number Diff line
@@ -102,7 +102,8 @@ extern bool have_bmi1; 
#define TCG_TARGET_HAS_mulsh_i32        0



#if TCG_TARGET_REG_BITS == 64

#define TCG_TARGET_HAS_trunc_shr_i64_i32 0

#define TCG_TARGET_HAS_extrl_i64_i32    0

#define TCG_TARGET_HAS_extrh_i64_i32    0

#define TCG_TARGET_HAS_div2_i64         1

#define TCG_TARGET_HAS_rot_i64          1

#define TCG_TARGET_HAS_ext8s_i64        1

tcg/ia64/tcg-target.h

+2 −1
Original line number Diff line number Diff line
@@ -160,7 +160,8 @@ typedef enum { 
#define TCG_TARGET_HAS_muluh_i64        0

#define TCG_TARGET_HAS_mulsh_i32        0

#define TCG_TARGET_HAS_mulsh_i64        0

#define TCG_TARGET_HAS_trunc_shr_i64_i32 0

#define TCG_TARGET_HAS_extrl_i64_i32    0

#define TCG_TARGET_HAS_extrh_i64_i32    0



#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)

#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)