Commit c54dc361 authored by Léo Grange's avatar Léo Grange

initial fx9860g board support using sh7750 implementation

parent 090d0bfd
obj-y += shix.o r2d.o
obj-y += shix.o r2d.o fx9860g.o
obj-y += sh7750.o sh7750_regnames.o
obj-y += sh7705_casio.o
obj-y += sh_pci.o
/*
* Casio fx9860g calculator board description.
*
* Copyright (c) 2015 Leo Grange
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/hw.h"
#include "hw/sh4/sh.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#define BIOS_FILENAME "bios.bin"
#define BIOS_ADDRESS 0xA0000000
static void fx9860g_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_model;
SuperHCPU *cpu;
struct SH7705CState *s;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
MemoryRegion *sdram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "SH7705-casio";
cpu = cpu_sh4_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
/* Allocate memory space */
memory_region_init_ram(rom, NULL, "fx9860g.rom", 0x4000, &error_abort);
vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(sysmem, 0x00000000, rom);
memory_region_init_ram(&sdram[0], NULL, "fx9860g.sdram", 0x01000000,
&error_abort);
vmstate_register_ram_global(&sdram[0]);
memory_region_add_subregion(sysmem, 0x08000000, &sdram[0]);
/* Register peripherals */
s = sh7705c_init(cpu, sysmem);
(void)s;
#if 0
/* Load BIOS in 0 (and access it through P2, 0xA0000000) */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
ret = load_image_targphys(bios_name, 0, 0x4000);
if (ret < 0 && !qtest_enabled()) {
error_report("Could not load SHIX bios '%s'", bios_name);
exit(1);
}
/* XXXXX Check success */
tc58128_init(s, "shix_linux_nand.bin", NULL);
#endif
fprintf(stderr, "Casio fx9860g board ready!\n");
}
static QEMUMachine fx9860g_machine = {
.name = "fx9860g",
.desc = "Casio fx9860g Calculator",
.init = fx9860g_init,
.is_default = 0,
};
static void fx9860g_machine_init(void)
{
qemu_register_machine(&fx9860g_machine);
}
machine_init(fx9860g_machine_init);
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......@@ -27,6 +27,29 @@ typedef struct {
int sh7750_register_io_device(struct SH7750State *s,
sh7750_io_device * device);
/* sh7705_casio.c */
struct SH7705CState;
struct SH7705CState *sh7705c_init(SuperHCPU *cpu, struct MemoryRegion *sysmem);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
uint16_t portamask_trigger;
uint16_t portbmask_trigger;
/* Return 0 if no action was taken */
int (*port_change_cb) (uint16_t porta, uint16_t portb,
uint16_t * periph_pdtra,
uint16_t * periph_portdira,
uint16_t * periph_pdtrb,
uint16_t * periph_portdirb);
} sh7705c_io_device;
int sh7705c_register_io_device(struct SH7705CState *s,
sh7705c_io_device * device);
qemu_irq sh7705c_irl(struct SH7705CState *s);
/* sh_timer.c */
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
......
......@@ -27,6 +27,7 @@
#define TYPE_SH7750R_CPU "sh7750r-" TYPE_SUPERH_CPU
#define TYPE_SH7751R_CPU "sh7751r-" TYPE_SUPERH_CPU
#define TYPE_SH7785_CPU "sh7785-" TYPE_SUPERH_CPU
#define TYPE_SH7705C_CPU "sh7705-casio-" TYPE_SUPERH_CPU
#define SUPERH_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
......
......@@ -230,6 +230,34 @@ static const TypeInfo sh7785_type_info = {
.instance_init = sh7785_cpu_initfn,
};
static void sh7705c_cpu_initfn(Object *obj)
{
SuperHCPU *cpu = SUPERH_CPU(obj);
CPUSH4State *env = &cpu->env;
env->id = SH_CPU_SH7705;
env->features = 0;
}
static void sh7705c_class_init(ObjectClass *oc, void *data)
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->name = "SH7705-casio";
/* this is a SH3, no PVR/PRR/CVR */
scc->pvr = 0x00000000;
scc->prr = 0x00000000;
scc->cvr = 0x00000000;
}
static const TypeInfo sh7705c_type_info = {
.name = TYPE_SH7705C_CPU,
.parent = TYPE_SUPERH_CPU,
.class_init = sh7705c_class_init,
.instance_init = sh7705c_cpu_initfn,
};
static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
......@@ -308,6 +336,7 @@ static void superh_cpu_register_types(void)
type_register_static(&sh7750r_type_info);
type_register_static(&sh7751r_type_info);
type_register_static(&sh7785_type_info);
type_register_static(&sh7705c_type_info);
}
type_init(superh_cpu_register_types)
......@@ -33,6 +33,7 @@
#define SH_CPU_SH7751 (1 << 3)
#define SH_CPU_SH7751R (1 << 4)
#define SH_CPU_SH7785 (1 << 5)
#define SH_CPU_SH7705 (1 << 6)
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
......
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