- 02 Sep, 2015 1 commit
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Léo Grange authored
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- 28 Aug, 2015 2 commits
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Laurent Vivier authored
guest_base must be used only in linux-user mode. Signed-off-by:
Laurent Vivier <laurent@vivier.eu> Message-id: 1440757421-9674-1-git-send-email-laurent@vivier.eu Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
Fix a capitalization error in the OS X build instructions; this was picked up in review of commit b352153f and intended to be corrected before I applied it, but I accidentally didn't include it. Signed-off-by:
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- 27 Aug, 2015 2 commits
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G 3 authored
qemu-doc.texi: Add information on compiling source code on Mac OS X Add information to the documentation on how to build QEMU on Mac OS X. Signed-off-by:
John Arbuckle <programmingkidx@gmail.com> Reviewed-by:
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Peter Maydell authored
tci patch queue # gpg: Signature made Wed 26 Aug 2015 19:51:07 BST using RSA key ID 677450AD # gpg: Good signature from "Stefan Weil <sw@weilnetz.de>" # gpg: aka "Stefan Weil <stefan.weil@weilnetz.de>" # gpg: aka "Stefan Weil <stefan.weil@bib.uni-mannheim.de>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4923 6FEA 75C9 5D69 8EC2 B78A E08C 21D5 6774 50AD * remotes/weil/tags/pull-tci-20150826: exec-all: Translate TCI return addresses backwards too Signed-off-by:
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- 26 Aug, 2015 3 commits
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Peter Crosthwaite authored
This subtraction of return addresses applies directly to TCI as well as host-TCG. This fixes Linux boots for at least Microblaze, CRIS, ARM and SH4 when using TCI. [sw: Removed indentation for preprocessor statement] [sw: The patch also fixes Linux boot for x86_64] Reviewed-by:
Stefan Weil <sw@weilnetz.de> Signed-off-by:
Peter Crosthwaite <crosthwaite.peter@gmail.com>
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Peter Maydell authored
vnc: fix memory corruption (CVE-2015-5225) # gpg: Signature made Wed 26 Aug 2015 17:37:21 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-cve-2015-5225-20150826-1: vnc: fix memory corruption (CVE-2015-5225) Signed-off-by: -
Gerd Hoffmann authored
The _cmp_bytes variable added by commit "bea60dd7 ui/vnc: fix potential memory corruption issues" can become negative. Result is (possibly exploitable) memory corruption. Reason for that is it uses the stride instead of bytes per scanline to apply limits. For the server surface is is actually fine. vnc creates that itself, there is never any padding and thus scanline length always equals stride. For the guest surface scanline length and stride are typically identical too, but it doesn't has to be that way. So add and use a new variable (guest_ll) for the guest scanline length. Also rename min_stride to line_bytes to make more clear what it actually is. Finally sprinkle in an assert() to make sure we never use a negative _cmp_bytes again. Reported-by:
范祚至(库特) <zuozhi.fzz@alibaba-inc.com> Reviewed-by:
P J P <ppandit@redhat.com> Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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- 25 Aug, 2015 20 commits
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Peter Maydell authored
target-arm queue: * add missing EL2/EL3 TLBI operations * add missing EL2/EL3 ATS operations * add missing EL2/EL3 registers * update Xilinx MAINTAINERS info * Xilinx: connect the four OCM banks # gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20150825-1: target-arm: Implement AArch64 TLBI operations on IPAs target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement missing EL2 TLBI operations target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order cputlb: Add functions for flushing TLB for a single MMU index target-arm: Implement AArch32 ATS1H* operations target-arm: Enable the AArch32 ATS12NSO ops target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 target-arm: Wire up AArch64 EL2 and EL3 address translation ops target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations target-arm: Implement missing ACTLR registers target-arm: Implement missing AFSR registers target-arm: Implement missing AMAIR registers target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers MAINTAINERS: Add ZynqMP to MAINTAINERS file MAINTAINERS: Update Xilinx Maintainership xlnx-zynqmp: Connect the four OCM banks Signed-off-by: -
Peter Maydell authored
Implement the AArch64 TLBI operations which take an intermediate physical address and invalidate stage 2 translations. Signed-off-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
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Peter Maydell authored
Implement the remaining stage 1 TLB invalidate operations visible from EL3. Signed-off-by:
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Peter Maydell authored
Implement the missing TLBI operations that exist only if EL2 is implemented. Signed-off-by:
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Peter Maydell authored
Now we have the ability to flush the TLB only for specific MMU indexes, update the AArch64 TLB maintenance instruction implementations to only flush the parts of the TLB they need to, rather than doing full flushes. We take the opportunity to remove some duplicate functions (the per-asid tlb ops work like the non-per-asid ones because we don't support flushing a TLB only by ASID) and to bring the function names in line with the architectural TLBI operation names. Signed-off-by:
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Peter Maydell authored
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the whole set of AArch64 TLBI regdefs is arranged in numeric order. Signed-off-by:
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Peter Maydell authored
Guest CPU TLB maintenance operations may be sufficiently specialized to only need to flush TLB entries corresponding to a particular MMU index. Implement cputlb functions for this, to avoid the inefficiency of flushing TLB entries which we don't need to. Signed-off-by:
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Peter Maydell authored
Implement the AArch32 ATS1H* operations which perform Hyp mode stage 1 translations. Signed-off-by:
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Peter Maydell authored
Apply the correct conditions in the ats_access() function for the ATS12NSO* address translation operations: * succeed at EL2 or EL3 * normal UNDEF trap from NS EL1 * trap to EL3 from S EL1 (only possible if EL3 is AArch64) (This change means they're now available in our EL3-supporting CPUs when they would previously always UNDEF.) Signed-off-by:
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Peter Maydell authored
Some coprocessor register access functions need to be able to report "trap to EL3 with an 'uncategorized' syndrome"; add the necessary CPAccessResult enum and handling for it. I don't currently know of any registers that need to trap to EL2 with the 'uncategorized' syndrome, but adding the _EL2 enum as well is trivial and fills in what would otherwise be an odd gap in the handling. Signed-off-by:
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Peter Maydell authored
Wire up the AArch64 EL2 and EL3 address translation operations (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some errors in the ats_write64() function in previously unused code that would have done the wrong kind of lookup for accesses from EL3 when SCR.NS==0. Signed-off-by:
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Peter Maydell authored
For EL2 stage 1 translations, there is no TTBR1. We were already handling this for 64-bit EL2; add the code to take the 'no TTBR1' code path for 64-bit EL2 as well. Signed-off-by:
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Peter Maydell authored
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and ACTLR_EL3, for consistency. Since we don't currently have any CPUs that need the EL2/EL3 versions to reset to non-zero values, implement as RAZ/WI. Signed-off-by:
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Peter Maydell authored
The AFSR registers are implementation dependent auxiliary fault status registers. We already implemented a RAZ/WI AFSR0_EL1 and AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency. Signed-off-by: -
Peter Maydell authored
The AMAIR registers are for providing auxiliary implementation defined memory attributes. We already implemented a RAZ/WI AMAIR_EL1; add the EL2 and EL3 versions for consistency. Signed-off-by:
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Peter Maydell authored
Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only two which we had implemented the 32-bit Secure equivalents of but not the 64-bit Secure versions. Signed-off-by:
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Alistair Francis authored
Add the Xilinx ZynqMP SoC and EP108 machine to the maintainers file. Signed-off-by:
Alistair Francis <alistair.francis@xilinx.com> Reviewed-by:
Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fed078103a0b02cfb3adadbe8e80e4420d554505.1436486024.git.alistair.francis@xilinx.com Signed-off-by:
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Alistair Francis authored
Peter C is leaving Xilinx, so update the maintainer list to point to Alistair and Edgar from Xilinx and Peter's personal email address. Signed-off-by:
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Alistair Francis authored
The Xilinx EP108 has four separate OCM banks which are located adjacent to each other. This patch adds the four banks to the ZynqMP SoC. Signed-off-by:
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Peter Maydell authored
queued tcg patches # gpg: Signature made Mon 24 Aug 2015 19:37:15 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20150824: linux-user: remove useless macros GUEST_BASE and RESERVED_VA linux-user: remove --enable-guest-base/--disable-guest-base tcg/aarch64: Use softmmu fast path for unaligned accesses tcg/s390: Use softmmu fast path for unaligned accesses tcg/ppc: Improve unaligned load/store handling on 64-bit backend tcg/i386: use softmmu fast path for unaligned accesses tcg: Remove tcg_gen_trunc_i64_i32 tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32 tcg: update README about size changing ops tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops tcg: implement real ext_i32_i64 and extu_i32_i64 ops tcg: don't abuse TCG type in tcg_gen_trunc_shr_i64_i32 tcg: rename trunc_shr_i32 into trunc_shr_i64_i32 tcg/optimize: allow constant to have copies tcg/optimize: track const/copy status separately tcg/optimize: add temp_is_const and temp_is_copy functions tcg/optimize: optimize temps tracking tcg/optimize: fix constant signedness Signed-off-by:
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- 24 Aug, 2015 12 commits
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Laurent Vivier authored
As we have removed CONFIG_USE_GUEST_BASE, we always use a guest base and the macros GUEST_BASE and RESERVED_VA become useless: replace them by their values. Reviewed-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Laurent Vivier authored
All tcg host architectures now support the guest base and as there is no real performance lost, it can be always enabled. Anyway, guest base use can be disabled lively by setting guest base to 0. CONFIG_USE_GUEST_BASE is defined as (USE_GUEST_BASE && USER_ONLY), it should have to be replaced by CONFIG_USER_ONLY in non CONFIG_USER_ONLY parts, but as some other parts are using !CONFIG_SOFTMMU I have chosen to use !CONFIG_SOFTMMU instead. Reviewed-by:
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Richard Henderson authored
Signed-off-by: -
Richard Henderson authored
Signed-off-by: -
Benjamin Herrenschmidt authored
Currently, we get to the slow path for any unaligned access in the backend, because we effectively preserve the bottom address bits below the alignment requirement when comparing with the TLB entry, so any non-0 bit there will cause the compare to fail. For the same number of instructions, we can instead add the access size - 1 to the address and stick to clearing all the bottom bits. That means that normal unaligned accesses will not fallback (the HW will handle them fine). Only when crossing a page boundary well we end up having a mismatch because we'll end up pointing to the next page which cannot possibly be in that same TLB entry. Reviewed-by:
Aurelien Jarno <aurelien@aurel32.net> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1437455978.5809.2.camel@kernel.crashing.org> Signed-off-by:
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Aurelien Jarno authored
Softmmu unaligned load/stores currently goes through through the slow path for two reasons: - to support unaligned access on host with strict alignement - to correctly handle accesses crossing pages x86 is only concerned by the second reason. Unaligned accesses are avoided by compilers, but are not uncommon. We therefore would like to see them going through the fast path, if they don't cross pages. For that we can use the fact that two adjacent TLB entries can't contain the same page. Therefore accessing the TLB entry corresponding to the first byte, but comparing its content to page address of the last byte ensures that we don't cross pages. We can do this check without adding more instructions in the TLB code (but increasing its length by one byte) by using the LEA instruction to combine the existing move with the size addition. On an x86-64 host, this gives a 3% boot time improvement for a powerpc guest and 4% for an x86-64 guest. [rth: Tidied calculation of the offset mask] Signed-off-by:
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Richard Henderson authored
Replacing it with tcg_gen_extrl_i64_i32. Signed-off-by: -
Richard Henderson authored
Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: -
Aurelien Jarno authored
Signed-off-by:
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Aurelien Jarno authored
They behave the same as ext32s_i64 and ext32u_i64 from the constant folding and zero propagation point of view, except that they can't be replaced by a mov, so we don't compute the affected value. Signed-off-by:
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Aurelien Jarno authored
Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a 32-bit value is always converted to a 64-bit value and not propagated through the register allocator or the optimizer. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Acked-by:
Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by:
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Aurelien Jarno authored
The tcg_gen_trunc_shr_i64_i32 function takes a 64-bit argument and returns a 32-bit value. Directly call tcg_gen_op3 with the correct types instead of calling tcg_gen_op3i_i32 and abusing the TCG types. Signed-off-by:
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